This invention relates to data processing memory units, and particularly to units which accept instruction transmitted through a data processing system along buses.
In a processing system wherein multiple elements such as processors and memory units are connected along a message bus, only one of the elements at a time can utilize the bus, to send a word on it. Accordingly, it is important that each transmission on the bus be a successful one. For example, if a processor sends an instruction to a memory unit, and it happens that the memory unit is busy with another instruction and cannot accept the new instruction, then the processor will have to try again later to send the instruction. A bus cycle has been wasted, and if on retry the memory unit is again busy with an instruction from another processor, then another cycle will be wasted. In addition, the processor has been unable to complete the issuance of its instruction and may be held up in its operation as a result.